Exception Modes

When an exception occurs, the CPU will change modes and the PC be forced to an exception vector. Thevector table starts from address zero with the reset vector and then has an exception vector every four bytes.

Exception Priority

ARM Core : Operating Modes

The ARM7 has seven different operating modes.

• User Mode
• Fast Interrupt Mode
• Interrupt Mode
• Supervisor Mode
• Abort Mode
• System Mode
• Undefined Mode

All modes other than User are privileged modes. These are used to servicehardware interrupts, exceptions, and software interrupts. Each privileged mode has an associated Saved Program Status Register (SPSR). This register is use to save the state of the Current Program Status Register (CPSR) of the task immediately before the exception occurs.

The system and user mode are combined in terms of register space.Both have the same register sets.System mode does not have any banked registers. It uses the User mode registers




In the THUMB state, eight general registers, the Program Counter (PC),Stack Pointer (SP), Link Register (LR), and Current Program Status Register (CPSR) are accessible.




PS: The PC,CSPR registers are not banked for the ARM or THUMB mode.
Only SP,LR and r7 to r14 for FIQ are banked.No FIQ banked registers in THUMB mode.

Register : CSPR

Current Program Status Register



The CPSR contains a number of flags which report and control the operation of the ARM7 CPU.

The top four bits of the CPSR contain the condition codes which are set by the CPU.
The lowest eight bits in the CPSR contain flags which may be set or cleared by the application code

ARM: Core : Registers

Registers are R0 to R15
Each is 32 bits wide

R0 to R12 are user registers

R13 to R15 are special
R13: stack pointer register(SP)
R14:Link register(LR)
R15:Program Counter(PC)

When a call is made to a function the return address is automatically stored in the link register and is immediately available on return from the function. This allows quick entry and return into a 'leaf’ function (a function that is not going to call further functions). If the function is part of a branch (i.e. it is going to call other functions) then the link register must be preserved on the stack (R13).

ARM Core : Pipeline

ARM7TDMI-S

• The ARM family member we’ll be using
• T – Thumb
• D – JTAG debug
• M – fast multiply
• I – EmbeddedICE macrocell
• S – synthesizable version

Pipeline is Three stage
Normally one instruction per cycle
If a branch is encountered, pipe is flushed and refilled

Very iMP:
the PC is running eight bytes ahead of the current instruction being executed, so
care must be taken when calculating offsets used in PC relative addressing..
eg: 0x4000 LDR PC,[PC,#4]
will load the contents of the address PC+4 into the PC. As the PC is running eight bytes ahead then the
contents of address 0x400C will be loaded into the PC and not 0x4004 as you might expect on first inspection.