ARM Core : Pipeline

ARM7TDMI-S

• The ARM family member we’ll be using
• T – Thumb
• D – JTAG debug
• M – fast multiply
• I – EmbeddedICE macrocell
• S – synthesizable version

Pipeline is Three stage
Normally one instruction per cycle
If a branch is encountered, pipe is flushed and refilled

Very iMP:
the PC is running eight bytes ahead of the current instruction being executed, so
care must be taken when calculating offsets used in PC relative addressing..
eg: 0x4000 LDR PC,[PC,#4]
will load the contents of the address PC+4 into the PC. As the PC is running eight bytes ahead then the
contents of address 0x400C will be loaded into the PC and not 0x4004 as you might expect on first inspection.